Fine-scale Burstiness Spells Bad News for Elasticity! Sadeka Islam1, Srikumar Venugopal1,2, Anna Liu1,3 (1. UNSW 2. IBM Research - Ireland 3. NICTA ) , , anna.liu@nict

Source URL: acmsocc.github.io

• Computing
• Burstiness
• Elasticity
• Cloud infrastructure
• Cloud computing
• Central processing unit

Reed Copsey, Jr. C Tech Development Corporation Blog - http://reedcopsey.com Twitter - http://twitter.com/ReedCopsey Copyright 2010 by Reed Copsey, Jr.

Source URL: reedcopsey.com

• Computing
• Parallel computing
• Computer architecture
• Multi-core processor
• Task parallelism
• Thread
• Data parallelism
• Multithreading
• Central processing unit
• Hyper-threading
• Task

Architectural Support for Software-Defined Metadata Processing Udit Dhawan1 C˘at˘alin Hri¸tcu2 Raphael Rubin1 Nikos Vasilakis1 Jonathan M. Smith1

Source URL: ic.ese.upenn.edu

• Computer memory
• Cache
• Computing
• Computer hardware
• Central processing unit
• Computer architecture
• Computer engineering
• CPU cache
• Locality of reference
• Draft:Cache memory

Computational Mass Spectrometry in a Reconfigurable Coherent Coprocessing Architecture Devi Sravanthi Yalamarthy∗ Joel Coburn† Rajesh K. Gupta†

Source URL: research.microsoft.com

• Computer architecture
• Computing
• Computer engineering
• OpenCL compute devices
• Parallel computing
• Central processing unit
• Coprocessor
• Heterogeneous computing
• Field-programmable gate array
• Graphics processing unit
• System on a chip
• Multi-core processor

Accurate emulation of CPU performance Tomasz Buchert1 Lucas Nussbaum2 1

Source URL: www.loria.fr

• Central processing unit
• Computing
• Engineering
• Computer performance
• Emulator
• Processor design
• CPU time

Efficient Software Implementation of Binary Field Arithmetic Using Vector Instruction Sets Diego F. Aranha Department of Computer Science University of Bras´ılia Joint work with

Source URL: caramba.loria.fr

• Computer architecture
• Computing
• X86 instructions
• Binary arithmetic
• Computer engineering
• Central processing unit
• Computer arithmetic
• Instruction set
• Streaming SIMD Extensions
• Bitwise operation
• Bit manipulation
• SSSE3

Elfen Scheduling: Fine-Grain Principled Borrowing from Latency-Critical Workloads using Simultaneous Multithreading Xi Yang† Stephen M. Blackburn† † Australian National University Abstract

Source URL: users.cecs.anu.edu.au

• Central processing unit
• Parallel computing
• Microprocessors
• Multithreading
• Scheduling
• Simultaneous multithreading
• Thread
• Task
• Monitor
• Latency
• Computer performance
• Micro-Threads

Procedure Call Standard for the ARM Architecture

Source URL: infocenter.arm.com

• Subroutines
• Central processing unit
• Acorn Computers
• ARM architecture
• Calling convention
• Application binary interface
• Pointer
• 64-bit computing
• Processor register
• Stack
• SIMD
• Instruction set

Modular Deductive Verification of Multiprocessor Hardware Designs Muralidaran Vijayaraghavan1 , Adam Chlipala1 , Arvind1 , and Nirav Dave2 1 MIT {vmurali,adamc,arvind}@csail.mit.edu

Source URL: plv.csail.mit.edu

• Computing
• Computer architecture
• Computer hardware
• Microprocessors
• Central processing unit
• IBM PC compatibles
• Instruction set architectures
• Microcomputers
• Program counter
• X86

Montage- und Inbetriebnahmeanleitung Installation and operating manual Zentrale CCU2 Central Control Unit CCU2

Source URL: www.eq-3.de